// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_nvme_pf_local_ctrl_reg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:12 Create file
// ******************************************************************************

#ifndef __HIPCIEC_NVME_PF_LOCAL_CTRL_REG_REG_OFFSET_FIELD_H__
#define __HIPCIEC_NVME_PF_LOCAL_CTRL_REG_REG_OFFSET_FIELD_H__

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_TIMEOUT_LEN    8
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_TIMEOUT_OFFSET 24
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_AMS_LEN        2
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_AMS_OFFSET     17
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_CQR_LEN        1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_CQR_OFFSET     16
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_MQES_LEN       16
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_MQES_OFFSET    0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_MPSMAX_LEN    4
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_MPSMAX_OFFSET 20
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_MPSMIN_LEN    4
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_MPSMIN_OFFSET 16
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_CSS_LEN       8
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_CSS_OFFSET    5
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NSSRS_LEN     1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NSSRS_OFFSET  4
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_DSTRD_LEN     4
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_DSTRD_OFFSET  0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_MJR_LEN    16
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_MJR_OFFSET 16
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_MNR_LEN    8
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_MNR_OFFSET 8
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_TER_LEN    8
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_TER_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_INTMS_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_INTMS_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_INTMC_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_INTMC_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_IOCQES_LEN    4
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_IOCQES_OFFSET 20
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_IOSQES_LEN    4
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_IOSQES_OFFSET 16
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_SHN_LEN       2
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_SHN_OFFSET    14
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_AMS_LEN       3
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_AMS_OFFSET    11
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_MPS_LEN       4
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_MPS_OFFSET    7
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_CSS_LEN       3
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_CSS_OFFSET    4
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ENABLE_LEN    1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ENABLE_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_PP_LEN       1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_PP_OFFSET    5
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NSSRO_LEN    1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NSSRO_OFFSET 4
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_SHST_LEN     2
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_SHST_OFFSET  2
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_CFS_LEN      1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_CFS_OFFSET   1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_READY_LEN    1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_READY_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NSSRC_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NSSRC_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ACQS_LEN    12
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ACQS_OFFSET 16
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ASQS_LEN    12
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ASQS_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ASQB_LOW_LEN    20
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ASQB_LOW_OFFSET 12

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ASQB_HIGH_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ASQB_HIGH_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ACQB_LOW_LEN    20
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ACQB_LOW_OFFSET 12

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ACQB_HIGH_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ACQB_HIGH_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_OFFSET_LEN    20
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_OFFSET_OFFSET 12
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BIR_LEN       3
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BIR_OFFSET    0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_SZ_LEN       20
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_SZ_OFFSET    12
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_SZU_LEN      4
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_SZU_OFFSET   8
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WDS_LEN      1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WDS_OFFSET   4
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_RDS_LEN      1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_RDS_OFFSET   3
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_LISTS_LEN    1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_LISTS_OFFSET 2
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_CQS_LEN      1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_CQS_OFFSET   1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_SQS_LEN      1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_SQS_OFFSET   0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_CC_INT_MASK_LEN      1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_CC_INT_MASK_OFFSET   7
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_AQA_INT_MASK_LEN     1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_AQA_INT_MASK_OFFSET  6
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_ASQ_INT_MASK_LEN     1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_ASQ_INT_MASK_OFFSET  5
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_NSSR_INT_MASK_LEN    1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_NSSR_INT_MASK_OFFSET 4
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_CC_INT_STS_LEN       1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_CC_INT_STS_OFFSET    3
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_AQA_INT_STS_LEN      1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_AQA_INT_STS_OFFSET   2
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_ASQ_INT_STS_LEN      1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_ASQ_INT_STS_OFFSET   1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_NSSR_INT_STS_LEN     1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_NSSR_INT_STS_OFFSET  0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_SQ_DB_INT_STS0_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_SQ_DB_INT_STS0_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_SQ_DB_INT_STS1_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_SQ_DB_INT_STS1_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_SQ_DB_INT_STS2_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_SQ_DB_INT_STS2_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_SQ_DB_INT_STS3_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_SQ_DB_INT_STS3_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_CQ_DB_INT_STS0_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_CQ_DB_INT_STS0_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_CQ_DB_INT_STS1_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_CQ_DB_INT_STS1_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_CQ_DB_INT_STS2_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_CQ_DB_INT_STS2_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_CQ_DB_INT_STS3_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_PF_CQ_DB_INT_STS3_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_INT_VECTOR_LEN      11
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_INT_VECTOR_OFFSET   2
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_INT_DEASSERT_LEN    1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_INT_DEASSERT_OFFSET 1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_INT_REQ_SET_LEN     1
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_INT_REQ_SET_OFFSET  0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_PF_CQ_DB_INT_MASK0_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_PF_CQ_DB_INT_MASK0_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_PF_CQ_DB_INT_MASK1_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_PF_CQ_DB_INT_MASK1_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_PF_CQ_DB_INT_MASK2_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_PF_CQ_DB_INT_MASK2_OFFSET 0

#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_PF_CQ_DB_INT_MASK3_LEN    32
#define HIPCIEC_NVME_PF_LOCAL_CTRL_REG_PF_CQ_DB_INT_MASK3_OFFSET 0

#endif // __HIPCIEC_NVME_PF_LOCAL_CTRL_REG_REG_OFFSET_FIELD_H__
